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1. general description the PCA9506 provides 40-bit parallel input/output (i/o) port expansion for i 2 c-bus applications organized in 5 banks of 8 i/os. at 5 v supply voltage, the outputs are capable of sourcing 10 ma and sinking 25 ma with a total package load of 800 ma to allow direct driving of 40 leds. any of the 40 i/o ports can be con?gured as an input or output. output ports are totem-pole and their logic state changes at the acknowledge (bank change). the device can be con?gured to have each input port to be masked in order to prevent it from generating interrupts when its state changes and to have the i/o data logic state to be inverted when read by the system master. an open-drain interrupt ( int) output pin allows monitoring of the input pins and is asserted each time a change occurs in one or several input ports (unless masked). the output enable ( oe) pin 3-states any i/o selected as output and can be used as an input signal to blink or dim leds (pwm with frequency > 80 hz and change duty cycle). the internal power-on reset (por) or hardware reset ( reset) pin initializes the 40 i/os as inputs. three address select pins con?gure one of 8 slave addresses. the PCA9506 is available in 56-pin tssop and hvqfn packages and is speci?ed over the - 40 cto+85 c industrial temperature range. 2. features n standard mode (100 khz) and fast mode (400 khz) compatible i 2 c-bus serial interface n 2.3 v to 5.5 v operation with 5.5 v tolerant i/os n 40 con?gurable i/o pins that default to inputs at power-up n outputs: u totem-pole (10 ma source, 25 ma sink) with controlled edge rate output structure u active low output enable ( oe) input pin 3-states all outputs u output state change on acknowledge n inputs: u open-drain active low interrupt ( int) output pin allows monitoring of logic level change of pins programmed as inputs u programmable interrupt mask control for input pins that do not require an interrupt when their states change u polarity inversion register allows inversion of the polarity of the i/o pins when read n active low reset ( reset) input pin resets device to power-up default state n 3 programmable address pins allowing 8 devices on the same bus PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int rev. 01 14 february 2006 product data sheet
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 2 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int n designed for live insertion u minimize line disturbance (i off and power-up 3-state) u signal transient rejection (50 ns noise ?lter and robust i 2 c-bus state machine) n low standby current n - 40 cto+85 c operation n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78, which exceeds 100 ma n offered in tssop56 and hvqfn56 packages 3. applications n servers n raid systems n industrial control n medical equipment n plcs n cell phones n gaming machines n instrumentation and test measurement 4. ordering information table 1: ordering information type number topside mark package name description version PCA9506dgg PCA9506dgg tssop56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm sot364-1 PCA9506bs PCA9506bs hvqfn56 plastic thermal enhanced very thin quad ?at package; no leads; 56 terminals; body 8 8 0.85 mm sot684-1
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 3 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 5. block diagram all i/os are set to inputs at power-up and reset. fig 1. block diagram of PCA9506 PCA9506 power-on reset 002aab492 v ss v dd reset i 2 c-bus control low pass input filters scl sda a0 a1 int oe 8-bit io0_0 io0_1 io0_2 io0_3 io0_4 io0_5 io0_6 io0_7 input/ output ports bank 0 write pulse 0 read pulse 0 bank 1 bank 2 bank 3 8-bit io4_0 io4_1 io4_2 io4_3 io4_4 io4_5 io4_6 io4_7 input/ output ports bank 4 write pulse 4 read pulse 4 a2 lp filter interrupt management
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 4 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int on power-up or reset, all registers return to default values. fig 2. simpli?ed schematic of io0_0 to io4_7 v dd iox_y v ss configuration port register data (cx[y]) output port register data (ox[y]) i/o configuration register dq ck q data from shift register write configuration pulse output port register dq ck data from shift register write pulse polarity inversion register dq ck data from shift register write polarity pulse esd protection diode input port register dq ck read pulse input port register data (ix[y]) int polarity register data (px[y]) 002aab493 interrupt management mx[y]
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 5 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 6. pinning information 6.1 pinning fig 3. pin con?guration for tssop56 PCA9506dgg sda reset scl int io0_0 io4_7 io0_1 io4_6 io0_2 io4_5 v ss v ss io0_3 io4_4 io0_4 io4_3 io0_5 io4_2 io0_6 io4_1 v ss v dd io0_7 io4_0 io1_0 io3_7 io1_1 io3_6 io1_2 io3_5 io1_3 io3_4 io1_4 io3_3 v dd v ss io1_5 io3_2 io1_6 io3_1 io1_7 io3_0 io2_0 io2_7 v ss v ss io2_1 io2_6 io2_2 io2_5 io2_3 io2_4 a0 oe a1 a2 002aab491 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 6 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 6.2 pin description fig 4. pin con?guration for hvqfn56 io1_5 v dd 002aab975 PCA9506bs transparent top view io3_0 io1_6 io1_7 io3_1 io3_2 v ss io1_4 io3_3 io1_3 io3_4 io1_2 io3_5 io1_1 io3_6 io1_0 io3_7 io0_7 io4_0 v ss v dd io0_6 io4_1 io0_5 io4_2 io0_4 io4_3 io2_0 v ss io2_1 io2_2 io2_3 a0 a1 a2 oe io2_4 io2_5 io2_6 v ss io2_7 io0_3 v ss io0_2 io0_1 io0_0 scl sda reset int io4_7 io4_6 io4_5 v ss io4_4 14 29 13 30 12 31 11 32 10 33 9 34 8 35 7 36 6 37 5 38 4 39 3 40 2 41 1 42 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 terminal 1 index area table 2: pin description symbol pin type description tssop56 hvqfn56 sda 1 50 i/o serial data line scl 2 51 i serial clock line io0_0 to io0_7 3, 4, 5, 7, 8, 9, 10, 12 52, 53, 54, 56, 1, 2, 3, 5 i/o input/output bank 0 io1_0 to io1_7 13, 14, 15, 16, 17, 19, 20, 21 6, 7, 8, 9, 10, 12, 13, 14 i/o input/output bank 1 io2_0 to io2_7 22, 24, 25, 26, 31, 32, 33, 35 15, 17, 18, 19, 24, 25, 26, 28 i/o input/output bank 2 io3_0 to io3_7 36, 37, 38, 40, 41, 42, 43, 44 29, 30, 31, 33, 34, 35, 36, 37 i/o input/output bank 3 io4_0 to io4_7 45, 47, 48, 49, 50, 52, 53, 54 38, 40, 41, 42, 43, 45, 46, 47 i/o input/output bank 4 v ss 6, 11, 23, 34, 39, 51 4, 16, 27, 32, 44, 55 [1] power supply ground supply voltage v dd 18, 46 11, 39 power supply supply voltage a0 27 20 i address input 0 a1 28 21 i address input 1 a2 29 22 i address input 2
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 7 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int [1] hvqfn package die supply ground is connected to both v ss pins and exposed center pad. v ss pins must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. 7. functional description refer to figure 1 bloc k diag r am of PCA9506 and figure 2 simpli? ed schematic of io0_0 to io4_7 . 7.1 device address following a start condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). the address of the PCA9506 is shown in figure 5 . slave address pins a2, a1, and a0 choose 1 of 8 slave addresses and need to be connected to v dd (1) or v ss (0). to conserve power, no internal pull-up resistors are incorporated on a2, a1, and a0. the last bit of the ?rst byte de?nes the operation to be performed. when set to logic 1 a read is selected, while a logic 0 selects a write operation. 7.2 command register following the successful acknowledgement of the slave address + r/ w bit, the bus master will send a byte to the PCA9506, which will be stored in the command register. oe 30 23 i active low output enable input int 55 48 o active low interrupt output reset 56 49 i active low reset input table 2: pin description continued symbol pin type description tssop56 hvqfn56 fig 5. PCA9506 address 002aab494 0 1 0 0 a2 a1 a0 r/w fixed slave address programmable fig 6. command register 002aab495 1 0 0 0 0 0 0 0 ai - d5 d4 d3 d2 d1 d0 auto-increment register number default at power-up or after reset
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 8 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int the lowest 6 bits are used as a pointer to determine which register will be accessed. the registers are: ? ip: input port registers (5 registers) ? op: output port registers (5 registers) ? pi: polarity inversion registers (5 registers) ? ioc: i/o con?guration registers (5 registers) ? msk: mask interrupt registers (5 registers) if the auto-increment ?ag is set (ai = 1), the 3 least signi?cant bits are automatically incremented after a read or write. this allows the user to program and/or read the 5 register banks sequentially. if more than 5 bytes of data are written and ai = 1, previous data in the selected registers will be overwritten. reserved registers are skipped and not accessed (refer to t ab le 3 ). if the auto-increment ?ag is cleared (ai = 0), the 3 least signi?cant bits are not incremented after data is read or written. during a read operation, the same register bank is read each time. during a write operation, data is written to the same register bank each time. only a command register code with the 5 least signi?cant bits equal to the 25 allowable values as de?ned in t ab le 3 are valid. reserved or unde?ned command codes must not be accessed for proper device functionality. at power-up, this register defaults to 0x80, with the ai bit set to logic 1, and the lowest 7 bits set to logic 0. during a write operation, the PCA9506 will acknowledge a byte sent to opx, pix, and iocx and mskx registers, but will not acknowledge a byte sent to the ipx registers since these are read-only registers.
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 9 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 7.3 register de?nitions table 3: register summary register # (hex) d5 d4 d3 d2 d1 d0 symbol access description input port registers 00 000000ip0 read only input port register bank 0 01 000001ip1 read only input port register bank 1 02 000010ip2 read only input port register bank 2 03 000011ip3 read only input port register bank 3 04 000100ip4 read only input port register bank 4 05 000101- - reserved for future use 06 000110- - reserved for future use 07 000111- - reserved for future use output port registers 08 001000op0 read/write output port register bank 0 09 001001op1 read/write output port register bank 1 0a 001010op2 read/write output port register bank 2 0b 001011op3 read/write output port register bank 3 0c 001100op4 read/write output port register bank 4 0d 001101- - reserved for future use 0e 001110- - reserved for future use 0f 001111- - reserved for future use polarity inversion registers 10 010000pi0 read/write polarity inversion register bank 0 11 010001pi1 read/write polarity inversion register bank 1 12 010010pi2 read/write polarity inversion register bank 2 13 010011pi3 read/write polarity inversion register bank 3 14 010100pi4 read/write polarity inversion register bank 4 15 010101- - reserved for future use 16 010110- - reserved for future use 17 010111- - reserved for future use i/o con?guration registers 18 011000 ioc0 read/write i/o con?guration register bank 0 19 011001 ioc1 read/write i/o con?guration register bank 1 1a 011010 ioc2 read/write i/o con?guration register bank 2 1b 011011 ioc3 read/write i/o con?guration register bank 3 1c 011100 ioc4 read/write i/o con?guration register bank 4 1d 011101- - reserved for future use 1e 011110- - reserved for future use 1f 011111- - reserved for future use
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 10 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 7.3.1 ip0 to ip4 - input port registers these registers are read-only. they re?ect the incoming logic levels of the port pins regardless of whether the pin is de?ned as an input or an output by the i/o con?guration register. if the corresponding px[y] bit in the pi registers is set to logic 0, or the inverted incoming logic levels if the corresponding px[y] bit in the pi register is set to logic 1. writes to these registers have no effect. the polarity inversion register can invert the logic states of the port pins. the polarity of the corresponding bit is inverted when px[y] bit in the pi register is set to logic 1. the polarity of the corresponding bit is not inverted when px[y] bits in the pi register is set to logic 0. mask interrupt registers 20 100000 msk0 read/write mask interrupt register bank 0 21 100001 msk1 read/write mask interrupt register bank 1 22 100010 msk2 read/write mask interrupt register bank 2 23 100011 msk3 read/write mask interrupt register bank 3 24 100100 msk4 read/write mask interrupt register bank 4 25 100101- - reserved for future use 26 100110- - reserved for future use 27 100111- - reserved for future use table 3: register summary continued register # (hex) d5 d4 d3 d2 d1 d0 symbol access description table 4: ip0 to ip4 - input port registers (address 00h to 04h) bit description legend: * default value x determined by the externally applied logic level. address register bit symbol access value description 00h ip0 7 to 0 i0[7:0] r xxxx xxxx* input port register bank 0 01h ip1 7 to 0 i1[7:0] r xxxx xxxx* input port register bank 1 02h ip2 7 to 0 i2[7:0] r xxxx xxxx* input port register bank 2 03h ip3 7 to 0 i3[7:0] r xxxx xxxx* input port register bank 3 04h ip4 7 to 0 i4[7:0] r xxxx xxxx* input port register bank 4
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 11 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 7.3.2 op0 to op4 - output port registers these registers re?ect the outgoing logic levels of the pins de?ned as outputs by the i/o con?guration register. bit values in these registers have no effect on pins de?ned as inputs. in turn, reads from these registers re?ect the values that are in the ?ip-?ops controlling the output selection, not the actual pin values. ox[y] = 0: iox_y = 0 if iox_y de?ned as output (cx[y] in ioc register = 0). ox[y] = 1: iox_y = 1 if iox_y de?ned as output (cx[y] in ioc register = 0). where x refers to the bank number (0 to 4); y refers to the bit number (0 to 7). 7.3.3 pi0 to pi4 - polarity inversion registers these registers allow inversion of the polarity of the corresponding input port register. px[y] = 0: the corresponding input port register data polarity is retained. px[y] = 1: the corresponding input port register data polarity is inverted. where x refers to the bank number (0 to 4); y refers to the bit number (0 to 7). table 5: op0 to op4 - output port registers (address 08h to 0ch) bit description legend: * default value. address register bit symbol access value description 08h op0 7 to 0 o0[7:0] r/w 0000 0000* output port register bank 0 09h op1 7 to 0 o1[7:0] r/w 0000 0000* output port register bank 1 0ah op2 7 to 0 o2[7:0] r/w 0000 0000* output port register bank 2 0bh op3 7 to 0 o3[7:0] r/w 0000 0000* output port register bank 3 0ch op4 7 to 0 o4[7:0] r/w 0000 0000* output port register bank 4 table 6: pi0 to pi4 - polarity inversion registers (address 10h to 14h) bit description legend: * default value. address register bit symbol access value description 10h pi0 7 to 0 p0[7:0] r/w 0000 0000* polarity inversion register bank 0 11h pi1 7 to 0 p1[7:0] r/w 0000 0000* polarity inversion register bank 1 12h pi2 7 to 0 p2[7:0] r/w 0000 0000* polarity inversion register bank 2 13h pi3 7 to 0 p3[7:0] r/w 0000 0000* polarity inversion register bank 3 14h pi4 7 to 0 p4[7:0] r/w 0000 0000* polarity inversion register bank 4
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 12 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 7.3.4 ioc0 to ioc4 - i/o con?guration registers these registers con?gure the direction of the i/o pins. cx[y] = 0: the corresponding port pin is an output. cx[y] = 1: the corresponding port pin is an input. where x refers to the bank number (0 to 4); y refers to the bit number (0 to 7). 7.3.5 msk0 to msk4 - mask interrupt registers these registers mask the interrupt due to a change in the i/o pins con?gured as inputs. x refers to the bank number (0 to 4); y refers to the bit number (0 to 7). mx[y] = 0: a level change at the i/o will generate an interrupt if iox_y de?ned as input (cx[y] in ioc register = 1). mx[y] = 1: a level change in the input port will not generate an interrupt if iox_y de?ned as input (cx[y] in ioc register = 1). 7.4 power-on reset when power is applied to v dd , an internal power-on reset (por) holds the PCA9506 in a reset condition until v dd has reached v por . at that point, the reset condition is released and the PCA9506 registers and i 2 c-bus state machine will initialize to their default states. thereafter, v dd must be lowered below 0.2 v to reset the device. 7.5 reset input a reset can be accomplished by holding the reset pin low for a minimum of t w(rst) . the PCA9506 registers and i 2 c-bus state machine will be held in their default states until the reset input is once again high. table 7: ioc0 to ioc4 - i/o con?guration registers (address 18h to 1ch) bit description legend: * default value. address register bit symbol access value description 18h ioc0 7 to 0 c0[7:0] r/w 1111 1111* i/o con?guration register bank 0 19h ioc1 7 to 0 c1[7:0] r/w 1111 1111* i/o con?guration register bank 1 1ah ioc2 7 to 0 c2[7:0] r/w 1111 1111* i/o con?guration register bank 2 1bh ioc3 7 to 0 c3[7:0] r/w 1111 1111* i/o con?guration register bank 3 1ch ioc4 7 to 0 c4[7:0] r/w 1111 1111* i/o con?guration register bank 4 table 8: msk0 to msk4 - mask interrupt registers (address 20h to 24h) bit description legend: * default value. address register bit symbol access value description 20h msk0 7 to 0 m0[7:0] r/w 1111 1111* mask interrupt register bank 0 21h msk1 7 to 0 m1[7:0] r/w 1111 1111* mask interrupt register bank 1 22h msk2 7 to 0 m2[7:0] r/w 1111 1111* mask interrupt register bank 2 23h msk3 7 to 0 m3[7:0] r/w 1111 1111* mask interrupt register bank 3 24h msk4 7 to 0 m4[7:0] r/w 1111 1111* mask interrupt register bank 4
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 13 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 7.6 interrupt output ( int) the open-drain active low interrupt is activated when one of the port pins changes state and the port pin is con?gured as an input and the interrupt on it is not masked. the interrupt is deactivated when the port pin input returns to its previous state or the input port register is read. remark: changing an i/o from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register. only a read of the input port register that contains the bit(s) image of the input(s) that generated the interrupt clears the interrupt condition. if more than one input register changed state before a read of the input port register is initiated, the interrupt is cleared when all the input registers containing all the inputs that changed are read. example: if io0_5, io2_3, and io3_7 change state at the same time, the interrupt is cleared only when inreg0, inreg2, and inreg3 are read. 7.7 output enable input ( oe) the active low output enable pin allows to enable or disable all the i/os at the same time. when a low level is applied to the oe pin, all the i/os con?gured as outputs are enabled and the logic value programmed in their respective op registers is applied to the pins. when a high level is applied to the oe pin, all the i/os con?gured as outputs are 3-stated. for applications requiring led blinking with brightness control, this pin can be used to control the brightness by applying a high frequency pwm signal on the oe pin. leds can be blinked using the output port registers and can be dimmed using the pwm signal on the oe pin thus controlling the brightness by adjusting the duty cycle. 7.8 live insertion the PCA9506 is fully speci?ed for live insertion applications using i off , power-up 3-states, robust state machine, and 50 ns noise ?lter. the i off circuitry disables the outputs, preventing damaging current back?ow through the device when it is powered down. the power-up 3-states circuitry places the outputs in the high-impedance state during power-up and power-down, which prevents driver con?ict and bus contention. the robust state machine does not respond until it sees a valid start condition and the 50 ns noise ?lter will ?lter out any insertion glitches. the PCA9506 will not cause corruption of active data on the bus, nor will the device be damaged or cause damage to devices already on the bus when similar featured devices are being used. 7.9 standby the PCA9506 goes into standby when the i 2 c-bus is idle. standby supply current is lower than 1 m a (typical).
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 14 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 8. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 8.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 7 ). 8.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is de?ned as the start condition (s). a low-to-high transition of the data line while the clock is high is de?ned as the stop condition (p) (see figure 8 ). 8.2 system con?guration a device generating a message is a transmitter; a device receiving is the receiver. the device that controls the message is the master' and the devices which are controlled by the master are the slaves' (see figure 9 ). fig 7. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 8. de?nition of start and stop conditions mba608 sda scl p stop condition sda scl s start condition
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 15 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 8.3 acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse; set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. 8.4 bus transactions data is transmitted to the PCA9506 registers using write byte transfers (see figure 11 , figure 12 , and figure 13 ). data is read from the PCA9506 registers using read and receive byte transfers (see figure 14 ). fig 9. system con?guration 002aaa966 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl i 2 c-bus multiplexer slave fig 10. acknowledgement on the i 2 c-bus 002aaa987 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 16 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int oe is low to observe a change in the outputs. if more than 5 bytes are written, previous data are overwritten. fig 11. write to the 5 output ports 002aab496 0 1 0 0 a2 a1 a0 0 slave address r/w s start condition sda a acknowledge from slave 10001000 command register ai = 1 a acknowledge from slave data bank 0 a acknowledge from slave data bank 1 a acknowledge from slave data bank 2 a acknowledge from slave data bank 3 p stop condition a acknowledge from slave output bank register bank 0 is selected data bank 4 a acknowledge from slave write to port data out from port t v(q) data valid bank 0 data valid bank 1 data valid bank 2 data valid bank 3 data valid bank 4 oe is low to observe a change in the outputs. two, three, or four adjacent banks can be programmed by using the auto-increment feature (ai = 1) and change at the corresponding output port becomes ef fective at each acknowledge. fig 12. write to a speci?c output port 002aab497 0 1 0 0 a2 a1 a0 0 slave address r/w s start condition sda a acknowledge from slave ai0001d2d1d0 a acknowledge from slave data bank x a acknowledge from slave p stop condition a write to port data out from port t v(q) data x valid
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 17 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int the programming becomes effective at the acknowledge. less than 5 bytes can be programmed by using this scheme. d5, d4, d3, d2, d1, d0 refers to the ?rst register to be programmed. if more than 5 bytes are written, previous data are overwritten (the sixth con?guration register will roll over to the ?rst add ressed con?guration register, the sixth polarity inversion register will roll over to the ?rst addressed polarity inversion register and the sixth mask interrupt regis ter will roll over to the ?rst addressed mask interrupt register). fig 13. write to the i/o con?guration, polarity inversion or mask interrupt registers 002aab498 0 1 0 0 a2 a1 a0 0 slave address r/w s start condition s da a acknowledge from slave 1 0 d5 d4 d3 d2 d1 d0 command register ai = 1 a acknowledge from slave data bank 0 a data bank 1 a data bank 2 a data bank 3 p stop condition a acknowledge from slave data bank 4 a acknowledge from slave acknowledge from slave d[5:0] = 01 0000 for polarity inversion register programming bank 0 d[5:0] = 01 1000 for configuration register programming bank 0 acknowledge from slave acknowledge from slave d[5:0] = 10 0000 for mask interrupt register programming bank 0 if ai = 0, the same register is read during the whole sequence. if ai = 1, the register value is incremented after each read. when the last register bank is read, it rolls over to the ?rst byte of the category (see category de?nition in section 7.2 command register ). the int signal is released only when the last register containing an input that changed has been read. for example, when io2_4 and io4_7 change at the same ti me and an input port registers read sequence is initiated, starting with ip0, int is released after ip4 is read (and not after ip2 is read). fig 14. read from input port, output port, i/o con?guration, polarity inversion or mask interrupt registers 002aab499 0 1 0 0 0 slave address r/w s start condition s da a acknowledge from slave 1 0 d5 d4 d3 d2 d1 d0 command register ai = 1 a acknowledge from slave a p stop condition a acknowledge from master d[5:0] = 00 1000 for output port register bank 0 d[5:0] = 01 0000 for polarity inversion register bank 0 sr repeated start condition 0 1 0 0 1 slave address r/w a acknowledge from slave d[5:0] = 01 1000 for configuration register bank 0 (cont.) at this moment master-transmitter becomes master-receiver , and slave-receiver becomes slave-transmitter. data data from register first byte register determined by d[5:0] a acknowledge from master data data from register second byte data data from register last byte no acknowledge from master d[5:0] = 00 0000 for input port register bank 0 d[5:0] = 10 0000 for mask interrupt register bank 0 a2 a1 a0 a2 a1 a0
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 18 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 9. application design-in information device address con?gured as 0100 000x for this example. io0_0, io0_2, io0_3, io1_0 to io3_7 are con?gured as outputs. io0_1, io0_4, io4_0 to io4_7 con?gured as inputs. fig 15. typical application PCA9506 io0_0 io0_1 scl sda v dd master controller scl sda 1.6 k w int 1.6 k w io0_2 v dd a2 a1 a0 5 v v dd reset oe gnd 1.1 k w (optional) oe int reset 2 k w 1.1 k w (optional) sub-system 1 (e.g., temp sensor) io0_3 int sub-system 2 (e.g., counter) reset controlled switch (e.g., cbt device) v dd a b enable sub-system 3 (e.g., alarm system) alarm io0_4 io0_5 io1_0 io3_7 io4_0 io4_7 24 led matrix alpha numeric keypad v ss 002aab500
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 19 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 10. limiting values 11. static characteristics table 9: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.5 +6 v v i input voltage v ss - 0.5 5.5 v i i input current - 20 ma v i/o(n) input/output voltage on any other pin v ss - 0.5 5.5 v v i/o(io0n) input/output voltage on pin io0_n v ss - 0.5 5.5 v i o(i/on) output current on an i/o pin - 20 +50 ma i dd supply current - 500 ma i ss ground supply current - 1100 ma p tot total power dissipation - 500 mw t stg storage temperature - 65 +150 c t amb ambient temperature operating - 40 +85 c t j junction temperature operating - 125 c storage - 150 c table 10: static characteristics v dd = 2.3 v to 5.5 v; v ss =0v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply v dd supply voltage 2.3 - 5.5 v i dd supply current operating mode; no load; f scl = 400 khz v dd = 2.3 v - 56 95 m a v dd = 3.3 v - 98 150 m a v dd = 5.5 v - 225 300 m a i stb standby current no load; f scl = 0 khz; i/o = inputs; v i =v dd v dd = 2.3 v - 0.15 11 m a v dd = 3.3 v - 0.25 12 m a v dd = 5.5 v - 0.75 15.5 m a v por power-on reset voltage [1] no load; v i =v dd or v ss - 1.70 2.0 v input scl; input/output sda v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd - 5.5 v i ol low-level output current v ol = 0.4 v 20 - - ma i l leakage current v i =v dd =v ss - 1- +1 m a c i input capacitance v i =v ss - 5 10 pf
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 20 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int [1] v dd must be lowered to 0.2 v in order to reset part. i/os v il low-level input voltage - 0.5 - +0.8 v v ih high-level input voltage 2 - 5.5 v i ol low-level output current v ol = 0.5 v v dd = 2.3 v 10 - - ma v dd = 3.0 v 12 - - ma v dd = 4.5 v 15 - - ma i ol(tot) total low-level output current v ol = 0.5 v; v dd = 4.5 v - - 0.6 a v oh high-level output voltage i oh = - 10 ma v dd = 2.3 v 1.6 - - v v dd = 3.0 v 2.3 - - v v dd = 4.5 v 4.0 - - v i lih high-level input leakage current v dd = 3.6 v; v i =v dd - 1- +1 m a i lil low-level input leakage current v dd = 5.5 v; v i =v ss - 1- +1 m a c i input capacitance - 6 7 pf c o output capacitance - 6 7 pf interrupt int i ol low-level output current v ol = 0.4 v 6 - - ma i oh high-level output current - 1- +1 m a c o output capacitance - 3.0 5 pf inputs reset and oe v il low-level input voltage - 0.5 - +0.8 v v ih high-level input voltage 2 - 5.5 v i li input leakage current - 1- +1 m a c i input capacitance - 3.0 5 pf inputs a0, a1, a2 v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd - 5.5 v i li input leakage current - 1- +1 m a c i input capacitance - 3.5 5 pf table 10: static characteristics continued v dd = 2.3 v to 5.5 v; v ss =0v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 21 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 12. dynamic characteristics [1] minimum scl clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either sda or s cl is held low for a minimum of 25 ms. disable bus time-out feature for dc operation. [2] t vd;ack = time for acknowledgement signal from scl low to sda (out) low. [3] t vd;dat = minimum time for sda data out to be valid following scl low. [4] a master device must internally provide a hold time of at least 300 ns for the sda signal (refer to the v il of the scl signal) in order to bridge the unde?ned region scls falling edge. table 11: dynamic characteristics symbol parameter conditions standard mode i 2 c-bus fast mode i 2 c-bus unit min max min max f scl scl clock frequency [1] 0 100 0 400 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - m s t hd;sta hold time (repeated) start condition 4.0 - 0.6 - m s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - m s t su;sto set-up time for stop condition 4.0 - 0.6 - m s t hd;dat data hold time 0 - 0 - ns t vd;ack data valid acknowledge time [2] 0.1 3.45 0.1 0.9 m s t vd;dat data valid time [3] 0.1 3.45 0.1 0.9 m s t su;dat data set-up time 250 - 100 - ns t low low period of the scl clock 4.7 - 1.3 - m s t high high period of the scl clock 4.0 - 0.6 - m s t f fall time of both sda and scl signals [4] [5] - 300 20 + 0.1c b [6] 300 ns t r rise time of both sda and scl signals [4] [5] - 1000 20 + 0.1c b [6] 300 ns t sp pulse width of spikes that must be suppressed by the input ?lter [7] -50-50ns port timing t en enable time output - 80 - 80 ns t dis disable time output - 40 - 40 ns t v(q) data output valid time - 250 - 250 ns t su(d) data input setup time 100 - 100 - ns t h(d) data input hold time 0.5 - 0.5 - m s interrupt timing t v(int_n) valid time on pin int_n - 4 - 4 m s t rst(int_n) reset time on pin int_n - 4 - 4 m s reset t w(rst) reset pulse width 4 - 4 - ns t rec(rst) reset recovery time 0 - 0 - ns t rst reset time 100 - 100 - ns
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 22 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int [5] the maximum t f for the sda and scl bus lines is speci?ed at 300 ns. the maximum fall time for the sda output stage t f is speci?ed at 250 ns. this allows series protection resistors to be connected between the sda and the scl pins and the sda/scl bus lines witho ut exceeding the maximum speci?ed t f . [6] c b = total capacitance of one bus line in pf. [7] input ?lters on the sda and scl inputs suppress noise spikes less than 50 ns. fig 16. de?nition of timing on the i 2 c-bus t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl 002aaa986 rise and fall times refer to v il and v ih . fig 17. i 2 c-bus timing diagram scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 002aab175 t su;sto protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) 1 /f scl t r t vd;dat
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 23 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 13. test information fig 18. reset timing sda scl 002aac018 t rst 50 % 30 % 50 % 50 % 50 % t rec(rst) t w(rst) reset iox_y output off start t rst ack or read cycle r l = load resistance c l = load capacitance includes jig and probe capacitance r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 19. test circuitry for switching times pulse generator v o c l 50 pf r l 500 w 002aac019 r t v i v dd dut 2v dd open v ss 500 w
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 24 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 14. package outline fig 20. package outline sot364-1 (tssop56) unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.2 0.1 8 0 o o 0.1 dimensions (mm are the original dimensions). notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. sot364-1 99-12-27 03-02-19 w m q a a 1 a 2 d l p q detail x e z e c l x (a ) 3 0.25 128 56 29 y pin 1 index b h 1.05 0.85 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 1 8.3 7.9 0.50 0.35 0.5 0.1 0.08 0.25 0.8 0.4 p e v m a a tssop56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm sot364-1 a max. 1.2 0 2.5 5 mm scale mo-153
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 25 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int fig 21. package outline sot684-1 (hvqfn56) 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm d h 4.45 4.15 y 1 4.45 4.15 e 1 6.5 e 2 6.5 0.30 0.18 0.05 0.00 8.1 7.9 8.1 7.9 0.05 0.1 dimensions (mm are the original dimensions) sot684-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot684-1 hvqfn56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 15 28 56 43 42 29 14 1 x d e c b a e 2 01-08-08 02-10-22 terminal 1 index area terminal 1 index area 1/2 e 1/2 e a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 26 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 15. handling information inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take precautions appropriate to handling mos devices. advice can be found in data handbook ic24 under handling mos devices . 16. soldering 16.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 16.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 cto270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 16.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results:
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 27 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 16.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 16.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. table 12: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 28 of 30 philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 17. abbreviations 18. revision history table 13: abbreviations acronym description cdm charged device model dut device under test esd electrostatic discharge hbm human body model ic integrated circuit i 2 c-bus inter ic bus led light emitting diode mm machine model plc programmable logic controller por power-on reset pwm pulse width modulation raid redundant array of independent disks table 14: revision history document id release date data sheet status change notice doc. number supersedes PCA9506_1 20060214 product data sheet - 9397 750 14939 -
philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 9397 750 14939 ? koninklijke philips electronics n.v. 2006. all rights reserved. product data sheet rev. 01 14 february 2006 29 of 30 19. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 20. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 21. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 22. trademarks notice all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of koninklijke philips electronics n.v. 23. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2006 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 14 february 2006 document number: 9397 750 14939 published in the netherlands philips semiconductors PCA9506 40-bit i 2 c-bus i/o port with reset, oe, and int 24. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 functional description . . . . . . . . . . . . . . . . . . . 7 7.1 device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 command register . . . . . . . . . . . . . . . . . . . . . . 7 7.3 register de?nitions . . . . . . . . . . . . . . . . . . . . . . 9 7.3.1 ip0 to ip4 - input port registers . . . . . . . . . . . 10 7.3.2 op0 to op4 - output port registers . . . . . . . . 11 7.3.3 pi0 to pi4 - polarity inversion registers. . . . . . 11 7.3.4 ioc0 to ioc4 - i/o con?guration registers. . . 12 7.3.5 msk0 to msk4 - mask interrupt registers . . . 12 7.4 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 12 7.5 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.6 interrupt output ( int) . . . . . . . . . . . . . . . . . . . 13 7.7 output enable input ( oe) . . . . . . . . . . . . . . . . 13 7.8 live insertion . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.9 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 characteristics of the i 2 c-bus. . . . . . . . . . . . . 14 8.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1.1 start and stop conditions . . . . . . . . . . . . . 14 8.2 system con?guration . . . . . . . . . . . . . . . . . . . 14 8.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.4 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 15 9 application design-in information . . . . . . . . . 18 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19 11 static characteristics. . . . . . . . . . . . . . . . . . . . 19 12 dynamic characteristics . . . . . . . . . . . . . . . . . 21 13 test information . . . . . . . . . . . . . . . . . . . . . . . . 23 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 24 15 handling information. . . . . . . . . . . . . . . . . . . . 26 16 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 16.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 16.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 26 16.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 26 16.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 27 16.5 package related soldering information . . . . . . 27 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 28 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . 28 19 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 29 20 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 21 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 22 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 23 contact information . . . . . . . . . . . . . . . . . . . . 29

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